Embedded Communications Research

LightLink: Powerline-to-Light Communication

A routine message is only useful if it reaches its recipient. LightLink investigates how power wiring, a controlled reserve and a local light receiver could reduce interruptions in non-critical updates.

2026 | Wits final-year research prototype
LightLink: Powerline-to-Light Communication

Overview

Imagine a maintenance update arriving in bursts at a fixed receiving point: the listener waits or asks for a repeat. LightLink explores whether suitable existing electrical wiring and a local visible-light receiver could support that non-critical service. The engineering problem is uneven delivery before the light transmitter. The work combines PLC characterisation, measurement-based FIFO sizing, ESP32 integration and a visitor-facing message studio. For Selah, it demonstrates practical skills in connecting hardware to usable software and testing the limits of a data path. It is university research, not a deployed mine communication product.

The Challenge

Problem

A high average powerline rate can hide multi-second delivery interruptions. A local optical transmitter needs a reserve of data, but excessive admission fills the queue and rejects arrivals.

Environment

Two university laboratories, domestic-scale cable arrangements and appliance conditions. The integrated comparison used a connected 65 W laptop charger and a 3 cm aligned optical bench link.

Goal

Characterise packet delivery, size a finite reserve and compare startup and sender-pacing modes without confusing adapter ratings, optical clock settings and useful received payload.

System Architecture

1

PLC TX and PLC RX

Commercial HomePlug adapters carry data over existing power wiring. A separate TL-PA7017 pair was used for characterisation; integrated tests used TL-PA4010 and TL-WPA4220 adapters.

2

Gateway / VLC TX

An ESP32-managed 105,472-byte FIFO waits for the declared 75% startup fill. Sender-side occupancy feedback targets 85% fill; nominal optical operation was 280 kbit/s.

3

VLC RX and recipient

An LED transmits to a photodiode receiver. Receiver observations reconstruct messages for display; the mobile demo confirms a source match and idle hardware before declaring delivery.

4

Mobile experience

Visitors draw, upload an image or write text in the browser. A queued bridge sends the prepared payload to the rig. Offline practice is explicitly simulated.

Technical Stack

Hardware
  • ›HomePlug PLC adapter pairs and domestic-scale cable arrangements
  • ›ESP32 gateway, LED transmitter and photodiode receiver
  • ›105,472-byte FIFO (103 KiB)
Firmware
  • ›Gated startup and occupancy-feedback sender admission
  • ›Nominal 280 kbit/s optical setting during integrated tests
  • ›Receiver records and buffer status kept distinct
Software
  • ›Python capture and analysis tools; packet-arrival evidence
  • ›A mobile message studio with queueing and verified reception
  • ›Separate sender and receiver bridges with the original RX dashboard

Results

MetricImmediate fixed-rate modeSelected gated-feedback mode
Mean received payload after 5 s204.91 kbit/s201.24 kbit/s
Buffer behaviourQueue saturated84.96% mean fill after 5 s
Recorded full-FIFO rejections19,719 across three complete captures0 across three complete captures

Engineering relevance to Selah

  • 1
    Facility monitoring needs a dependable path from an embedded device to the person using its data. LightLink demonstrates measurement, queue management and integration skills relevant to that work.
  • 2
    Potential future use: non-critical maintenance or status messages at a fixed receiving point, subject to cable, optical, equipment and site-approval assessment.
  • 3
    PLC characterisation: Nduvho E. Ramashia. VLC subsystem: Israel Chiloane. Buffer requirements, integration and analysis: shared. Supervisor: Prof. Ling Cheng. This is a university project, not a Selah client deployment.

Technical Insights & Lessons

1

Integrated comparison: five modes, three 60-second repeats per mode, 65 W charger present, iron off, 3 cm optical separation, 0-degree alignment, 280 kbit/s nominal. The results are bench observations, not service guarantees.

2

The PLC survey contains 31 arrival records over 5,393 seconds; its longest gap was approximately 5.46 seconds. The 2.5-second reserve is an empirical sizing target under ideal recovery, not independently validated outage coverage.

3

The 300 kbit/s sizing basis and tested optical maximum are distinct from the 280 kbit/s nominal setting and 201.24 kbit/s measured useful payload.

4

The selected feedback mode favours reserve and admission headroom over the slightly higher output of immediate fixed-rate buffering. Five zero-output counter windows remained among 327 post-startup windows.

5

No mine deployment, speech playback quality, mine-wide coverage, installation savings or timestamped end-to-end latency was demonstrated. Site-specific validation is needed before operational use.

Technologies Used
ESP32PLCVLCPythonEmbedded C/C++Feedback control
Year2026
Duration2026 | Wits final-year research prototype
CategoryEmbedded Communications Research
View on GitHub

Ready to Add Real-Time Monitoring to Your Facility?

Tell us about your facility, environment, and what you need to measure. We'll scope a system that works - sensors, firmware, dashboard, and deployment.